The present invention relates to input circuit and out-put circuit for transferring data within a semiconductor integrated circuit at a much higher speed.
As the multimedia applications have been expanding in recent years, improvement of operating performance of a semiconductor device has become more and more pressing task to be fulfilled. That is to say, an ideal operating speed of a semiconductor device has been steeply rising, and desired power consumption of the device has been drastically falling. In particular, a system, like an image processor, which is intended to process a large quantity of data at a high speed, strongly needs a semiconductor device operative at an extremely high speed. Generally speaking, in order to operate a device at a high speed, data should be transferred within the device at a high speed, which in turn requires some high-speed data transfer technique. High-speed-transfer-related technology includes speeding up the operation of an input/output circuit and adopting a high-speed transfer standard for a data bus. Also, input circuits of various types have become popular lately. Examples of those circuits include: a differential input circuit for comparing a voltage of a signal received to a reference voltage and amplifying the voltage of the received signal based on the difference therebetween; and a differential input circuit for receiving differential (or complementary), signals and outputting a single signal.
If an output circuit for outputting a data signal has a push-pull configuration, however, it is very difficult to match its output impedance, or its output current, when each driver transistor outputs H-level data with its output impedance or current when each transistor outputs L-level data. In this specification, “L-level data” and “H-level” data means data with a voltage level defined as logically low (i.e., the voltage level is lower than a certain reference level) and data with a voltage level defined as logically high (i.e., the voltage level is higher than the reference level), respectively. Also, if an output circuit for outputting a data signal is a pull-up output circuit including a pull-up resistor connected to the output thereof, it is hard to equalize a current flowing through the resistor with that flowing through a transistor for outputting the data signal.
In view of the state of the art, the length of a transition interval from L to H level of a data signal is not equal to that of its transition interval from H to L level. Thus, an interval during which the voltage level of such a data signal received by a receiver is defined as logically high judging from the reference voltage is not equal in length to an interval during which that of the data signal is defined as logically low. If such a data signal is transferred and held at irregular intervals in response to a clock signal with regular pulses, then skewing is more likely to happen. As a result, the receiver might operate erroneously, thus interfering with the speedup of a system. The higher the intended speed of a system is, the more seriously such skewing is affecting. In general, the length of a data transition interval is on the orders of several hundreds picoseconds to several nanoseconds. Thus, if a high-speed operation should be performed responsive to a clock signal at a frequency of several hundreds megahertz (i.e., one cycle of the clock signal is several nanoseconds), then the data transition intervals account for as much as several tens percent of one cycle of the clock signal. Thus, skewing is very likely to happen in such a situation.